The present invention relates to a semiconductor memory device, and more particularly to a voltage control circuit, a voltage control method and a semiconductor memory device having the voltage control circuit which can reduce leakage currents and improve precharge performance.
Generally, a semiconductor memory device enters into an active state in response to an active command and activates a given word line. Subsequently, the semiconductor memory device delivers cell data corresponding to the word line to outside through bit lines or stores the data delivered from outside on the corresponding cell through the bit lines.
When the semiconductor memory device enters a standby state in response to a precharge command, the bit line is precharged with bit line precharge voltage VBLP. Typically, the bit line precharge voltage has a half level of a core voltage VCORE, which is a cell data voltage.
Such semiconductor memory devices exhibit process defects such as a gate residue, which leads to producing a resistive short in the word line and in the bit line and in generating a current path. That is, when the semiconductor memory device is in the standby state, the standby current provided to the bit line can be leaked to a ground line via a subword line which is short-circuited.
Conventionally, a bleed voltage VBLEED lower than the bit line precharge voltage VBLP is applied to precharge the bit lines BL, BLB shown in FIG. 1, in order to reduce the leakage current generated by the gate residue.
More specifically, the leakage current to the ground line can be reduced by applying the bleed voltage VBLEED which is made lower than the bit line precharge voltage VBLP by a prescribed voltage level to the bit lines BL, BLB using a voltage control circuit 1, as shown in thick dotted lines in FIG. 1.
Herein, the voltage control circuit 1 is comprised of a bleeder resistor which enables constant currents to be flowed irrespective of loads in order to prevent the voltage from being changed due to variations of the load current.
The bleeder resistor can be comprised of a PMOS transistor or a NMOS transistor, wherein a gate is biased to a ground voltage VSS in a case of the PMOS transistor and a gate is biased to the power supply voltage VDD in a case of the NMOS transistor, in order to be maintained in a turn-on state.
On the other hands, the semiconductor memory device is divided into a core region and a peripheral region. The core region is divided into a memory cell array region 2, a subword line driver region 3, a sense amp array region 4 and a sense amp control region 5 which is a cross region of the subword line driver region 3 and the sense amp array region 4. The voltage control circuit 1 is arranged within the sense amp control region 5.
According to such prior art, since the voltage control circuit 1 is arranged in the core region, there is a problem in that the size of the other transistor controlling the core is reduced, which can result in decreasing the performance of the core.
Moreover, considering that, for example, a metal pitch is 1.2 μm, the number of a sense amp array is 33 per bank, and there are 4 banks with respect to a metal line 6 arranged to apply the bleed voltage VBLEED, a problem can occur when a length of the metal line 6 is increased by 80 μm and thus the total area of the semiconductor memory device is increased.
Further, since the voltage control circuit 1 can not control the bleed voltage VBLEED, it is difficult to satisfy an amount of leakage current required for certain specification, thereby reducing product yield of the semiconductor memory device. For example, if the amount of leakage current in the standby state can not satisfy specification defined in IDD2P, it is difficult to control the bleed voltage VBLEED, which results in poor yield of the semiconductor memory device.
Since the bleed voltage VBLEED lower than the precharge voltage VBLP is applied as the precharge voltage irrespective of the active state and the standby state, then the time to precharge the bit lines BL, BLB in the active state is increased, which necessarily results in lowering the precharge performance.